Design and Analysis of Full Adder Using Different Low Power Techniques

The complexity in VLSI design increases with an increase in the level of integration. Due to the portable electronics area, power and delay have become the most important factors. In conventional CMOS design, the area, power and delay are more compared to other Low power techniques. In this paper full adder is designed using different low power techniques, such as, conventional CMOS, GDI, Modified GDI and hybrid full adders which has a combination of GDI, TG, XOR, XNOR and pass transistor logic. All the designs are compared for area, power and delay. The power delay product graph is drawn for all the designs. The design and simulation are done in MENTOR GRAPHICS TOOL in 180 nm technology.

Author(s): Bavusaheb kunchanur, Swapna Srinivasan

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